Digital Systems Lab 15

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Lab 15: Register Control Logic

Breaking Lab 15 Into Parts

You may not be able to finish this circuit if you do not have a solid plan for building the circuit. Here are the steps you should take to build the circuit.

  • First, build the FSM and put LEDs on the output of each flip-flop. Once you press the load button, you’ll see the progression from 11 -> 01 -> 00. Use a clock of 1-2 Hz for now. CLR pins go to VCC for now.
  • Next, implement the Moore machine outputs and check that those are correct by putting LEDs on the OS and CS output signals. Once you press the load button, you’ll see the progression from 01 -> 10 -> 00. Keep the same slow clock and CLR/VCC for now. Be sure that CS is zero when the load button is pressed!
  • Next, implement the addition step. Pay attention to the order of MSB/LSB on the registers and the adder chip. You should see that numbers continuously add together, although there is no overflow logic yet. A slow clock is OK for now, and set CLR to VCC still.
  • Finally, implement the overflow and reset clearing logic. Now your CLR pins will go to the overflow/reset signal, rather than VCC. Increase the clock frequency to at least 100 Hz.

Other Tips

  • Keep notes of what’s connected to each logic gate
  • Use wire colors to stay organized


Watch/read the following resources prior to attending this lab. This information will teach you how to use lab equipment and provide suggestions and technical tips for successfully completing the lab.

  • Textbook: Section 12.2
  • Video: Register adder circuit
  • Because many students don’t understand what the circuit is supposed to do, below is an embed of a simulation of the circuit built in CircuitVerse. You can play around with the simulation to see how it works. (Note that a lot of the parts in CircuitVerse are different from the 7400 chips, so this does not have a 1:1 correlation with what you will build in lab.)