ATmega328P Serial Peripheral Interface (SPI)

Section 10.2 ATmega328P Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) protocol on the ATmega328P is capable of full-duplex synchronous communication using a maximum of four wires. The Arduino can be configured as either a primary or a secondary, and can send data bytes either MSB first or LSB first. [16.3]

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The ATmega328P SPI protocol uses four defined logic signals, described below. Each of the signals is associated with a particular pin on port B. (Please note that there is an inconsistency between the pin names and the descriptions, refer to the preface of this book for more information.)

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SCK, pin PB5: serial clock (output from primary)
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MISO, pin PB4: primary data input, secondary data output
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MOSI, pin PB3: primary data output, secondary data input
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~SS, pin PB2: secondary select (active-LOW, output from primary)
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Individual primary and secondary devices should be connected as shown in Figure 10.2.1. (Refer to Subsection 10.2.3 to see how to connect multiple secondary devices with a single primary.) A primary device must contain a shift register and clock generator (the ATmega328P contains this hardware). A secondary must contain a synchronous shift register. As a data byte is transmitted from the primary to the secondary along the MOSI line, the data that was previously stored in the secondary’s shift register transmits from the secondary to the primary along the MISO line. In this manner, data is simultaneously transmitted and received (full-duplex).

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$On the left the primary is depicted in dashed lines. The components include a data bus that can communicate bidirectionally with a shift register and a clock generator that connects to the CLK input of the shift register. On the right the secondary is depicted in dashed lines. The components include a data bus that can communicate bidirectionally with a shift register. MOSI is defined as the output of the primary shift register and the input of the secondary shift register. MISO is defiend as the output of the secondary shift register and the input of the primary shift register. SCK is defined as the clock generator output that connects also to the secondary shift register CLK input. ~SS is a signal depicted as an output from the primary and input to the secondary.$

Figure 10.2.1. SPI primary-secondary connection diagram.

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The SPI protocol (independent of its use on the ATmega328P microcontroller) has a number of advantages and disadvantages. Advantages of SPI include

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full-duplex communication,
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simple hardware requirements (including no requirement for a secondary address assignment as in TWI),
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no requirement for built-in hardware as the protocol can be achieved by “bit-banging” (manually setting and clearing I/O pins to achieve the desired signals),
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no protocol-level limit to clock speed (this is only limited by hardware and microcontroller clock speeds),
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no protocol-level limit to the number of bits that can be sent at a time (however the ATmega328P architecture limits to 8 bits at a time), and
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typically lower power consumption than protocols such as TWI due to the absence of pull-up resistors on secondary devices.
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Disadvantages of SPI include

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more pins are required in SPI than in USART or TWI protocols,
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capable of only short-distance communication ([16.10]),
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lack of error-checking protocol, and
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lack of secondary device acknowledgement (the primary could send data to nowhere and not realize it).
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Subsection 10.2.1 ATmega328P in Primary Mode

The microcontroller can be configured as a primary device by setting the primary/secondary select (MSTR) bit in the SPI control register (SPCR). The microcontroller hardware will override any data direction on the MISO pin to ensure that it is an input pin. The other three SPI pin data directions can be set at the programmer’s discretion.

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If the microcontroller won’t be transmitting any data, the MOSI pin need not be used. However, as the primary device asserts the clock signal, the SCK pin will likely need to be connected and configured as an output pin. The secondary select pin (~SS) must either be configured as an output pin or as an input pin that is held HIGH. (This is true regardless of whether or not the secondary select pin is necessarily used in a circuit design!) Typically, it is simpler to ensure the secondary select pin is an output pin by setting the appropriate bit in DDRB.

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Subsection 10.2.2 ATmega328P in Secondary Mode

The microcontroller can be configured as a secondary device by ensuring that the primary/secondary select (MSTR) bit in the SPI control register (SPCR) is cleared. The microcontroller hardware will override any data direction on the MOSI, ~SS, and SCK pins to ensure that they are input pins. The MISO pin data direction can be set at the programmer’s discretion.

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SPI will be activated and capable of receiving data when the ~SS bit is held LOW. When held HIGH, the SPI hardware will not receive any incoming data.

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Subsection 10.2.3 Multiple Secondary Devices

Multiple secondary devices can be supported with SPI. This can be accomplished with an independent secondary configuration as shown in Figure 10.2.2. Independent secondary devices all require their own secondary select signal. Therefore using many independent secondary devices can require a a large number of I/O pins. However, each individual secondary can be written to in one write cycle.

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The primary is depicted as a rectangle with pins SCK, MOSI, MISO, ~SS1, ~SS2, ~SS3, and ~SS4. There are four secondaries, each depicted as a rectangle with pins SCK, MOSI, MISO, and ~SS. The SCK pin from the primary writes to each of the secondary SCK pins. The MOSI pin from the primary writes to each of the secondary MOSI pins. The MISO pin from the primary reads from each of the secondary MISO pins. ~SS1 on the primary connects to one of the secondary ~SS pins. ~SS2 on the primary connects to a different one of the secondary ~SS pins. ~SS3 on the primary connects to a different one of the secondary ~SS pins. ~SS4 on the primary connects to the last of the secondary ~SS pins. — Figure 10.2.2. Independent secondary configuration in SPI.
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Multiple secondary devices can also be connected with a daisy-chained configuration as shown in Figure 10.2.3. Daisy-chained secondary devices have the output of one secondary feeding into the input of the next, sharing a common secondary select signal. This reduces the number of I/O pins required to write to multiple secondary devices. However, it increases the write time requirement as sending data to the $m^{\textrm{th}}$ secondary requires the data to be shifted through each of the $m-1$ preceding secondary devices.

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The primary is depicted as a rectangle with pins SCK, MOSI, MISO, and ~SS. There are four secondaries, each depicted as a rectangle with pins SCK, MOSI, MISO, and ~SS. The SCK pin from the primary writes to each of the secondary SCK pins. The MOSI pin from the primary writes to MOSI on the first secondary. MISO from the first secondary writes to MOSI on the second secondary. MISO on the second secondary writes to MOSI on the third secondary. MISO on the third secondary writes to MOSI on the fourth secondary. MISO on the fourth secondary writes to MISO on the primary. The ~SS pin from the primary writes to each of the secondary ~SS pins. — Figure 10.2.3. Daisy-chained secondary configuration in SPI.
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Subsection 10.2.4 Clock Polarity and Phase

Clock polarity indicates the idle value of the clock signal. When idle, the SCK will be kept LOW if the clock polarity (CPOL) bit in the SPI control register (SPCR) is 0. Otherwise, if CPOL is 1, the clock signal will be kept HIGH when idle. A timing diagram depicting the value on SCK is shown in Figure 10.2.4 for both values of CPOL.

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Top graph (CPOL = 0): a signal starts out idling LOW, then has 8 rising and falling edges before idling back to LOW. Bottom graph (CPOL = 1): a signal starts out idling HIGH, then has 8 falling and rising edges before idling back to HIGH. — Figure 10.2.4. SPI clock signal (`SCK`) for different values of `CPOL`.
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The clock phase, configured by the clock phase (CPHA) bit in the SPI control register (SPCR), indicates the edge of SCK that’s used to sample data from the receive pin. When CHPA is 0, data will be sampled on the leading edge (which will be a rising edge if CPOL is 0 and a falling edge if CPOL is 1). When CHPA is 1, data will be sampled on the trailing edge (which will be a falling edge if CPOL is 0 and a rising edge if CPOL is 1). The combination of CPOL and CPHA settings is known as the SPI mode. These four modes are summarized in Table 10.2.5.

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Table 10.2.5. SPI modes of operation.

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SPI Mode	`CPOL`	`CPHA`	Data Sample
0	`0`	`0`	Rising edge
1	`0`	`1`	Falling edge
2	`1`	`0`	Falling edge
3	`1`	`1`	Rising edge

When two microcontrollers are communicating to each other using the SPI protocol, each must have the same values configured for CPOL and CPHA. When a single microcontroller is communicating with a piece of hardware (say, a shift register chip), then the datasheet must be consulted to determine the values to set for CPOL and CPHA based on the piece of hardware.

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