Section 6.2 ADC Architectures
There are many different hardware approaches to realizing an ADC. Each architecture has tradeoffs between size, resolution, and data processing time. While only three architectures are outlined here, there are many other possibilities that exist to convert analog signals to digital values. [16.9]
All architectures of ADC discussed in this textbook use a circuit element known as an analog comparator as a building block. An analog comparator is a circuit element that has two inputs, \(V_p\) (positive input) and \(V_n\) (negative input), and one output \(V_{out}\text{.}\) The output becomes equal to \(V_{ref}\) if \(V_p \geq V_n\text{.}\) Otherwise, the output will be equal to GND. The circuit symbol of a comparator is shown in Figure 6.2.1.
Subsection 6.2.1 Flash-Type (Direct Conversion) ADC
A flash-type ADC uses analog comparators to quantize an analog input signal. A circuit known as a voltage divider (composed of multiple identical resistors wired up in series between the reference voltage and GND) is used to divide the reference voltages into \(2^n\) voltages. Each of these divisions are connected to the inverting input of an analog comparator. The non-inverting input of the analog comparator is connected to the analog signal. In this manner, an \(n\)-bit flash-type ADC would require \(2^n-1\) analog comparators.
Each comparator output (\(V_{out,x}\)) becomes equal to the reference voltage (\(V_{ref}\)) if the inequality in (6.2.1) is satisfied, where \(V_{in}\) is the input voltage (applied to the non-inverting input), \(x\) is the number of the comparator, and \(n\) is the number of bits of system resolution.
\begin{equation}
V_{in} \geq V_{ref} \times \left(\frac{x}{2^n}\right)\tag{6.2.1}
\end{equation}
A 3-bit flash-type ADC (which requires seven analog comparators) is shown in Figure 6.2.2. The voltage divider is represented with eight resistors. These create fractional values of the reference voltage (VCC), each of which is connected to a comparator’s inverting input pin.
The output of each comparator is connected to a priority encoder, which converts the quantized signal into a binary output value that can be stored in a data register.
Flash ADCs are quick. Because they are able to process every bit of data simultaneously, they require no sample-and-hold circuitry and would only need a single clock cycle to compute the output (assuming the comparators and encoder are fast enough to have a stable output value at that time). However, they consume relatively high amounts of power and also require \(2^n-1\) comparators, which means they require a form factor that is unreasonably large for high resolution data converters. (A 10-bit ADC would require 1023 analog comparators!)
Subsection 6.2.2 Successive Approximation Register (SAR) ADC
A successive approximation register works by comparing the analog input to half of the value of \(V_{ref}\text{,}\) then depending on the result, comparing in intervals of half the remaining difference until the final result is determined.
A process flow of how a 4-bit SAR ADC calculates values is shown in Figure 6.2.3. The analog input value is first compared with one half of the maximum value. If the analog input is larger than this value (indicated by the letter L), then it is compared to successively larger approximations of the value. If the analog input is smaller than this value (indicated by the letter S), then it is compared to successively smaller approximations of the value until settling on the result.
An SAR ADC requires a properly calibrated digital to analog converter (DAC, Section 6.3), but only requires a single analog comparator, so the form factor is relatively small. It takes \(n\) clock cycles to compute a final result, where \(n\) is equal to the number of bits of system resolution. At any particular instant in time, an SAR ADC will consume less power than an otherwise equivalent flash-type ADC. [16.12]
Subsection 6.2.3 Pipelined ADC
A pipelined ADC has \(q\) stages, where \(q\) is equal to the total device resolution divided by stage resolution. Each stage (which has \(m\) bits of resolution) uses an \(m\)-bit flash-type ADC to calculate \(m\) bits of the result at a time. For example, Figure 6.2.4 depicts the block diagram of a 12-bit pipelined ADC using four 3-bit flash stages.
The first stage of the pipelined ADC calculates the first 3 most significant bits of the result. This is then subtracted from the input value, and then the next 3 significant bits are calculated. This process iterates until the final result has been calculated, giving an output of the form \(\underline{A_1B_1C_1}~\underline{A_2B_2C_2}~\underline{A_3B_3C_3}~\underline{A_4B_4C_4}\text{.}\) In this manner, a pipelined ADC requires \(q\) clock cycles to compute the output.
