ATmega328P Timer/Counter Modes of Operation

Section 9.4 ATmega328P Timer/Counter Modes of Operation

Using the two output compare units on each timer/counter, the timer/counter can carry out one of its many modes of operation. These are

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normal mode,
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clear timer on compare match (CTC) mode,
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fast PWM mode,
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phase-correct PWM mode, and
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phase- and frequency-correct PWM mode (only available on timer/counter 1).
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Normal and CTC modes will be discussed below. The PWM modes of operation will be discussed in Section 9.6.

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Subsection 9.4.1 Normal Mode

In normal mode, the timer/counter unit will count up (increment) from BOTTOM to MAX. When the value in TCNTn reaches MAX, the counter overflows and restarts from BOTTOM. In normal mode, the timer/counter overflow flag TOVn will be set when the value in the timer/counter register becomes zero. A timing diagram depicting the value stored in TCNTn over time in normal mode is shown in Figure 9.4.1.

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$The x-axis depicts time and the y-axis goes between BOTTOM and MAX. The value in the timer/counter increments from BOTTOM to MAX, then abruptly overflows back to BOTTOM. This repeats at regular intervals. Each time the value of the timer/counter overflows, the TOVn interrupt flag is set.$

Figure 9.4.1. Timing diagram of the value stored in register TCNTn when operating in normal mode.

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The amount of time it takes for the timer/counter to overflow is defined by (9.4.1), where $N$ is the value of the timer/counter prescaler selected by configuring the clock select (CS) bits in timer/counter control register B (TCCRnB), $n$ is the resolution of the timer/counter (either 8 or 16), and $f_{CLK,I/O}$ is the frequency of the I/O clock.

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\begin{equation} T_{normal} = \frac{N \times 2^n}{f_{CLK,I/O}}\tag{9.4.1} \end{equation}

In this manner, normal mode can be used to generate regularly occurring interrupts using the timer/counter overflow flag. Using the output compare unit to generate a waveform in normal mode is not recommended.

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Subsection 9.4.2 Clear Timer on Compare Match (CTC) Mode

In clear timer on compare match (CTC) mode, the timer/counter unit will count up (increment) from BOTTOM to TOP, where TOP is equal to the value stored in the output compare A register (OCRnA). (Timer/counter 1 has the additional possibility to have TOP equal to the value stored in the input capture register (ICR1) instead of from OCR1A.) Upon reaching the value of TOP, the timer/counter will clear to zero and continue incrementing again.

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The amount of time it takes for the timer/counter to reach the TOP value is defined by (9.4.2).

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\begin{equation} T_{CTC} = \frac{N \times (\texttt{TOP} + 1)}{f_{CLK,I/O}}\tag{9.4.2} \end{equation}

Because the value of TOP is configureable (as well as the value of the prescaler), the period of operation is much more flexible than what is possible in normal mode.

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Upon reaching the value of TOP, the output compare flag A (OCFnA) will be set. (In timer/counter 1 counting to ICR1, the input capture flag ICF1 will be set.) In this manner, CTC mode can be used to generate regularly occurring interrupts using the timer/counter compare match A interrupt (or the input capture event interrupt).

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Compare match B interrupts can also be enabled, as the output compare flag B (OCFnB) will be set when the value stored in TCNTn is equal to the value stored in OCRnB. The interval of time between compare match B interrupts will be the same as the interval of time between compare match A interrupts, with the interval of time controlled by the value of TOP. For example, if compare match A interrupts occur every 6 ms, compare match B interrupts will also occur every 6 ms. If the two output compare registers (OCRnA and OCRnB) contain different values, then there will be a time offset between the triggering of each individual compare match interrupt.

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A timing diagram of a timer/counter in CTC mode is shown in Figure 9.4.2. The timer/counter compare match interrupt flags are both set at periodic intervals, controlled by the value stored in register OCRnA.

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$The x-axis depicts time and the y-axis goes between BOTTOM and MAX. The value in the timer/counter incrments from BOTTOM to OCRnA (which is between BOTTOM and MAX and greater than OCRnB), then abruptly resets back to BOTTOM. This repeats at regular intervals. Each time the value of the timer/counter reaches the value in OCRnB, the OCnB interrupt flag is set. Each time the value of the timer/counter reaches the value in OCRnA, the OCnA interrupt flag is set.$

Figure 9.4.2. Timing diagram of the value stored in register TCNTn and the timer/counter compare match interrupt flags when operating in CTC mode.

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Note that the value of TOP can be changed in software (it does not need to be set to a static value that never changes). This would modify the timing of any interrupts or output compare waveforms (described below). If a new value is stored as TOP while the timer/counter is higher than that value, it will be unable to trigger a compare match that cycle. The timer/counter will increment to MAX, reset to zero, and then compare on the next round.

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In CTC mode, the overflow flag TOVn is set only when the timer/counter unit counts from MAX to BOTTOM. As this typically does not happen in CTC mode, it is recommended not to rely on overflow interrupts when using a timer/counter in CTC mode.

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CTC mode can also be used to generate square waves with 50% duty cycle either of the output compare pins (OCnx). This occurs when the compare output mode (COMnx) bits are configured to cause the output compare pin to toggle on a compare match and are configured as output pins in the corresponding data direction register. The period of the square wave is defined by (9.4.3).

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\begin{equation} T_{OCnx} = \frac{2 \times N \times (\texttt{TOP} + 1)}{f_{CLK,I/O}}\tag{9.4.3} \end{equation}

The multiplication by 2 is due to the compare pin toggling each time the timer/counter reaches TOP. Therefore, it will take two cycles of reaching TOP before the compare pin reaches its initial state, completing one full oscillation.

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Similar to how compare match A and compare match B interrupts will occur with the same periodicity in CTC mode, square waves generated on each compare pin will also have the same period. However, depending on the values stored in each output compare register, there may be a time offset between each waveform.

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An example of waveforms generated on both output compare pins of a single timer/counter using CTC mode is shown in Figure 9.4.3.

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The x-axis depicts time and the y-axis goes between BOTTOM and MAX. The value in the timer/counter incrments from BOTTOM to OCRnA (which is between BOTTOM and MAX and greater than OCRnB), then abruptly resets back to BOTTOM. This repeats at regular intervals. Each time the value of the timer/counter reaches the value in OCRnB, the value on the OCnB pin toggles. Each time the value of the timer/counter reaches the value in OCRnA, the value on OCnA pin toggles. — Figure 9.4.3. Timing diagram of the value stored in register `TCNTn` and the timer/counter compare match interrupt flags when operating in CTC mode.
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