Microcontrollers

The ATmega328P has 26 different interrupt sources, listed in Table 8.1.1. This interrupt vector table defines the address in program memory where the pointer to each interrupt service routine will be stored. For example, if the PCINT0 interrupt service routine is stored in program memory at a starting address of 0x0AF2, that address value (0x0AF2) will be stored in program memory at location 0x0006. When that interrupt is triggered, the program counter will load the address stored in location 0x0006 and execute the instructions at that address. The end of an interrupt should always contain a return from interrupt (RETI) instruction, causing the program counter to go back to its previous location.

If an interrupt is enabled, but no ISR is defined, the program counter will still load the address stored in the corresponding memory location. It’s possible that the value stored in that memory location will lead to an area of program memory with no legitimate code to execute. This can cause a program to stop working once the interrupt is triggered. If an interrupt is enabled, the corresponding ISR must be defined in software.

The priority of interrupt servicing is defined by the interrupt vector table. If two or more interrupts are triggered at the exact same instant, the interrupt with the lowest vector number will be serviced first, followed by the next highest vector, and so on, until all interrupts have been serviced.

Reset is a special category of interrupt on the ATmega328P. It is the highest priority ISR and cannot be disabled.

There are four different reset sources on the ATmega328P microcontroller. The source of the most recent reset can be determined by reading information from the MCU status register (MCUSR).

At times, it is useful to mask (disable) or unmask (enable) interrupts. Interrupts can be globally masked by clearing the global interrupt enable flag (I) in SREG, as described in Subsection 4.3.1. (This process occurs automatically when an ISR is invoked on the ATmega328P to prohibit one interrupt from interrupting another.) Interrupts can be globally enabled by setting the global interrupt enable flag in SREG. (This occurs automatically after an ISR has concluded upon receiving the RETI instruction.)

Some interrupts are nonmaskable. The reset interrupt is nonmaskable; it cannot be masked even if the I flag in SREG is cleared.

It can be important to globally mask interrupts while performing particular tasks that cannot be interrupted. These tasks include configuring peripherals (such as the ADC, timer/counters, external interrupts, and pin-change interrupts) and when reading from or writing to the “16-bit” registers on the ATmega328P (including TCNT1 and other registers associated with timer/counter 1). The following code demonstrates masking interrupts in C.

int main(void) {
    cli(); // globally mask interrupts
    // peripheral configuration code
    sei(); // globally enable interrupts

    while (1) {
        // program code
    }
}

Each individual interrupt can be enabled or disabled using its corresponding configuration or setup register. For example, enabling the ADC interrupt requires setting the ADC interrupt enable (ADIE) bit in the ADC control and status register A (ADCSRA).

As previously mentioned, an ISR is serviced in order of priority, with lower vector locations being serviced first if two or more interrupts are invoked simultaneously. When the first ISR concludes, the ISR with the next level of priority will be invoked, and so on until all interrupts that were triggered have been serviced.

If an interrupt is triggered when another interrupt is being serviced, a status flag will be set to notify the microcontroller to service it once the current interrupt has concluded. Because the I flag in SREG is automatically cleared upon entering an ISR, that means that an interrupt will not be serviced while another interrupt is being serviced. (This can be manually overridden but is strongly discouraged.) If the same interrupt is triggered more than once when interrupts are globally masked (either because the cli() function was used or because an interrupt is currently being serviced), that interrupt will only be serviced once when interrupts are globally enabled again.

Because interrupts are typically used to temporarily halt normal operations to deal with an important event, and because it would be bad for the same interrupt to be triggered multiple times while interrupts are globally masked, it’s important to ensure that each ISR is written to execute as quickly as possible. It’s also important to ensure that interrupts will not be globally masked for long periods of time as program code executes. If one or more ISR requires extensive processing tasks, a backlog of interrupts can pile up, with repeated interrupts unable to be serviced at all. This can cause cascading errors with program operation.

It’s important to note that the value of SREG is not automatically stored when an ISR is invoked by an interrupt request. This means that any critical functionality of the microcontroller (for example, performing conditional and/or Boolean operations to execute control flow logic) will be affected. The value of SREG must therefore be stored upon executing an ISR and retrieved upon concluding an ISR.