Section 11.1 Sleep Modes
There are six sleep modes available on the ATmega328P. The sleep modes reduce power consumption by disabling both the CPU clock (\(clk_{CPU}\)) and flash clock (\(clk_{FLASH}\)) and stopping the execution of program instructions. Each individual sleep mode can furthermore disable one or more of the additional peripheral clock modules (as depicted in Figure 9.1.1). If an embedded system is designed to exhibit some kind of idle time (when instructions do not need to be executed), then a sleep mode can be used to reduce power consumption during those times.
Each of the sleep modes has its own wake-up source to exit the sleep mode. Each sleep mode may also have different peripheral clock modules activated to enable certain functionality as needed.
To enter a sleep mode, the sleep enable (
SE) bit in the sleep mode control register (SMCR) must be set with the sleep mode select (SM) bits configured as desired. This must be followed by a sleep command (SLEEP instruction in assembly). If an enabled interrupt corresponding to a wake-up source occurs when the microcontroller is in a sleep mode, the microcontroller will exit the sleep mode, halt for four clock cycles, and then continue executing the program code at the address following the SLEEP instruction.
If the brown-out detection (BOD) unit is enabled in the extended fuse byte, it is recommended to disable the BOD when the microcontroller is in a sleep mode. This can be accomplished using the MCU control register (
MCUCR).
Subsection 11.1.1 Idle Mode
Idle mode stops the CPU clock and flash clock (the ADC, I/O, and asynchronous clock modules are all enabled in idle mode). This allows the use of SPI, USART, analog comparator, ADC, TWI, timer/counters, watchdog timer, and system interrupts. Wake-up sources in idle mode include
-
external and pin-change interrupts,
-
TWI address match,
-
timer/counter 2,
-
SPM and EEPROM ready,
-
ADC,
-
WDT, and
-
other I/O.
Subsection 11.1.2 ADC Noise Reduction Mode
ADC noise reduction mode stops the CPU clock, I/O clock, and flash clock (the ADC and asynchronous clock modules are both enabled in ADC noise reduction mode). The peripherals that can continue to run under this restriction are the ADC, external interrupts, TWI, timer/counter 2 (clocked asynchronously), and the watchdog timer. As is indicated from the name, shutting down superfluous clock signals leads to lower noise in the ADC, which leads to more accurate results. Wake-up sources in ADC noise reduction mode include
-
external and pin-change interrupts,
-
TWI address match,
-
timer/counter 2,
-
SPM and EEPROM ready,
-
ADC, and
-
WDT.
Subsection 11.1.3 Power-Down and Power-Save Modes
Power-down mode shuts off all generated clocks, allowing only asynchronous modules to run. Wake-up sources in power-down mode include
-
external and pin-change interrupts,
-
TWI address match, and
-
WDT.
Power-save mode is virtually identical to power-down mode, except that timer/counter 2, if enabled and clocked asynchronously, will continue running during sleep. (Power-save mode does not shut down the asynchronous clock module.) Timer/counter 2 can additionally be used as a wake-up source in power-save mode.
Subsection 11.1.4 Standby and Extended Standby Modes
When clocked from an external source, standby mode can be used; it is identical to power-down mode except that the external oscillator is kept running. Wake-up sources in standby mode include
-
external and pin-change interrupts,
-
TWI address match, and
-
WDT.
Similarly to power-down and power-save modes, extended standby mode is virtually identical to power-save except that an external source is used to clock the system and the eternal clock will continue running during sleep. (Extended standby mode does not shut down the asynchronous clock module.) Therefore, timer/counter 2 can be used as a wake-up source in this sleep mode.
