Section 10.4 ATmega328P Two-Wire Interface (TWI)
Two-wire interface (TWI), also referred to as inter-integrated circuit (I\(^2\)C), is a serial protocol used to connect with one or more secondary devices (connected as shown in Figure 10.4.1, note the use of pull-up resistors on both signal lines) using only two I/O pins. One wire is a bidirectional data line called
SDA, which indicates that TWI is capable of half-duplex communication. The other wire, SCL (also bidirectional), carries the clock signal, indicating that TWI is a synchronous communication protocol. These I/O pins are listed below.
Subsection 10.4.1 TWI Modules
The TWI hardware on the ATmega328P consists of several modules that work together to operate the communication system. This is depicted as a block diagram in Figure 10.4.2.
The two pins
SCL and SDA interface the microcontroller with external devices. The bus interface unit contains four parts:
-
The TWI data and address shift register (
TWDR), which contains the address of data bytes to be transmitted, or the address of data bytes that have been received. -
The
START/STOPcontroller, which generates and detectsSTARTandSTOPbits used for framing the received and transmitted data. -
Spike suppression, which filters out short bursts of data that may otherwise interfere with serial communication.
-
The arbitration detection unit, which monitors communications to ensure that only one primary is communicating at a time in a multi-primary system.
The bit rate generator controls the period of the clock signal on
SCL when the device is operating in primary mode. The bit rate is stored in the TWI bit rate register (TWBR), and together with the TWI prescaler (TWPS) bits they control the period defined by (10.4.1), where \(N\) is the value of the prescaler.
\begin{equation}
T_{SCL} = \frac{16 + (2 \times \texttt{TWBR} \times N)}{f_{CLK,I/O}}\tag{10.4.1}
\end{equation}
The address match unit uses a comparator to check that the received address byte matches the 7-bit address given in the TWI address register (
TWAR).
Finally, the control unit monitors the TWI bus and generates signals in response to the settings that have been detected by all of the other units. The TWI status register (
TWSR) contains data corresponding to the status of the most recently executed communication operation on the bus. The TWI control register (TWCR) contains the bus specification and settings.
Subsection 10.4.2 TWI Communication Process
While TWI has the advantage of using fewer wires than SPI communication, the drawback is in the complexity of using the TWI protocol. Communication begins when the primary transmits a
START bit followed by the 7-bit address of the secondary with which it intends to communicate and a bit indicating a read or write operation. (To be assigned a unique secondary address for a TWI-compatible device, a fee must be paid to NXP Semiconductors.) The corresponding secondary device (if it is properly connected to the interface bus) then sends an acknowledge bit, which the primary can use to ensure that it is indeed communicating with the correct device. The primary then continues to send a clock signal while either transmitting messages to the secondary or receiving data from the secondary. A STOP bit is transmitted when communication with the secondary is complete.
Subsection 10.4.3 TWI Status Codes
Multiple status codes exist for all TWI communication modes (primary transmit, primary receive, secondary transmit, and secondary receive). These codes give information about the status of the bus and connected hardware. They can be used to generate error messages, or to stop program flow if proper handshaking and acknowledgement between primary and secondary has not been successful.
