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Microcontrollers

Section 3.2 Instructions

The model microcontroller introduced in this chapter has seven defined instructions. Therefore, a minimum of 3 bits in the instruction are necessary to differentiate between each of the instructions opcodes. Four bits will be used to express each opcode so that each instruction has a word size of 8 bits.
The model microcontroller instructions are each defined below.

Subsection 3.2.1 IN: Load data from input to register

The IN instruction loads data from an input device to one of the registers. In order to carry out this instruction, the designation of the input device (I/O(A)) as well as the designation of the destination register (Rd) need to be known. This instruction does not require use of the ALU.

Subsection 3.2.2 OUT: Store data from register to output

The OUT instruction takes data from a source register and sends it to one of the output devices. In order to carry out this instruction, the designation of the output device (I/O) as well as the designation of the source register (Rr) need to be known. This instruction does not require use of the ALU.

Subsection 3.2.3 MOV: Copy data from one register to another

The MOV instruction takes data from a source register and copies it into a destination register. In order to carry out this instruction, the designations of both the source (Rr) and the destination (Rd) registers need to be known. This instruction does not require use of the ALU.

Subsection 3.2.4 ADD: Add data from register Rr to Rd and store in Rd

The ADD instruction takes data from two registers, adds the contents, and stores the sum into a destination register. In order to carry out this instruction, the designations of both the source (Rr) and the destination (Rd) registers need to be known.
As depicted in FigureΒ 3.1.1, the ADD instruction operates in hardware as described below.

Subsection 3.2.5 SUB: Subtract data in register Rr from Rd and store in Rd

The SUB instruction takes data from a source register, subtracts it from the contents of the destination register, and then stores the result into a destination register. In order to carry out this instruction, the designations of both the source (Rr) and the destination (Rd) registers need to be known. The order of operands is particularly important as subtraction is not a commutative operation.
As depicted in FigureΒ 3.1.1, the SUB instruction operates in hardware as described below.

Subsection 3.2.6 AND: Logical AND data in register Rr with Rd and store in Rd

The AND instruction takes data from a source register, performs a logical AND operation with the contents of the destination register, and then stores the result into a destination register. In order to carry out this instruction, the designations of both the source (Rr) and the destination (Rd) registers need to be known.
As depicted in FigureΒ 3.1.1, the AND instruction operates in hardware as described below.

Subsection 3.2.7 OR: Logical OR data in register Rr with Rd and store in Rd

The OR instruction takes data from a source register, performs a logical OR operation with the contents of the destination register, and then stores the result into a destination register. In order to carry out this instruction, the designations of both the source (Rr) and the destination (Rd) registers need to be known.
As depicted in FigureΒ 3.1.1, the OR instruction operates in hardware as described below.