Section 3.2 Instructions
The model microcontroller introduced in this chapter has seven defined instructions. Therefore, a minimum of 3 bits in the instruction are necessary to differentiate between each of the instructions opcodes. Four bits will be used to express each opcode so that each instruction has a word size of 8 bits.
The model microcontroller instructions are each defined below.
Subsection 3.2.1 IN: Load data from input to register
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Mnemonic:
IN -
Opcode:
0000 -
Machine instruction:
0000 AAdd -
Assembly instruction:
IN Rd, A -
Register-transfer language:
Rd β I/O(A)
The
IN instruction loads data from an input device to one of the registers. In order to carry out this instruction, the designation of the input device (I/O(A)) as well as the designation of the destination register (Rd) need to be known. This instruction does not require use of the ALU.
Subsection 3.2.2 OUT: Store data from register to output
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Mnemonic:
OUT -
Opcode:
0001 -
Machine instruction:
0001 rrAA -
Assembly instruction:
OUT A, Rr -
Register-transfer language:
I/O β Rr
The
OUT instruction takes data from a source register and sends it to one of the output devices. In order to carry out this instruction, the designation of the output device (I/O) as well as the designation of the source register (Rr) need to be known. This instruction does not require use of the ALU.
Subsection 3.2.3 MOV: Copy data from one register to another
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Mnemonic:
MOV -
Opcode:
0010 -
Machine instruction:
0010 rrdd -
Assembly instruction:
MOV Rd, Rr -
Register-transfer language:
Rd β Rr
The
MOV instruction takes data from a source register and copies it into a destination register. In order to carry out this instruction, the designations of both the source (Rr) and the destination (Rd) registers need to be known. This instruction does not require use of the ALU.
Subsection 3.2.4 ADD: Add data from register Rr to Rd and store in Rd
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Mnemonic:
ADD -
Opcode:
0011 -
Machine instruction:
0011 rrdd -
Assembly instruction:
ADD Rd, Rr -
Register-transfer language:
Rd β Rr + Rd
The
ADD instruction takes data from two registers, adds the contents, and stores the sum into a destination register. In order to carry out this instruction, the designations of both the source (Rr) and the destination (Rd) registers need to be known.
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Opcode 00 is sent to the comparator, which outputs a value of 0.
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MUX2 output: Cin, which enters the adder
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MUX1 output: B, which enters the adder
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A also enters the adder
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MUX3 output: sum
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The carry is sent as Cout
Subsection 3.2.5 SUB: Subtract data in register Rr from Rd and store in Rd
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Mnemonic:
SUB -
Opcode:
0100 -
Machine instruction:
0100 rrdd -
Assembly instruction:
SUB Rd, Rr -
Register-transfer language:
Rd β Rr - Rd
The
SUB instruction takes data from a source register, subtracts it from the contents of the destination register, and then stores the result into a destination register. In order to carry out this instruction, the designations of both the source (Rr) and the destination (Rd) registers need to be known. The order of operands is particularly important as subtraction is not a commutative operation.
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Opcode 01 is sent to the comparator, which outputs a value of 1
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MUX2 output: 1, which enters the adder
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MUX1 output: Bβ, which enters the adder (this generates the twoβs complement value of B)
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A also enters the adder
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MUX3 output: (A + (-B))
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The carry is sent as Cout
Subsection 3.2.6 AND: Logical AND data in register Rr with Rd and store in Rd
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Mnemonic:
AND -
Opcode:
0101 -
Machine instruction:
0101 rrdd -
Assembly instruction:
AND Rd, Rr -
Register-transfer language:
Rd β Rr Β· Rd
The
AND instruction takes data from a source register, performs a logical AND operation with the contents of the destination register, and then stores the result into a destination register. In order to carry out this instruction, the designations of both the source (Rr) and the destination (Rd) registers need to be known.
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Opcode 10 is sent to the comparator, which outputs a value of 0
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A and B both go to the AND gate
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MUX3 output: A Β· B
Subsection 3.2.7 OR: Logical OR data in register Rr with Rd and store in Rd
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Mnemonic:
Or -
Opcode:
0110 -
Machine instruction:
0110 rrdd -
Assembly instruction:
OR Rd, Rr -
Register-transfer language:
Rd β Rr V Rd
The
OR instruction takes data from a source register, performs a logical OR operation with the contents of the destination register, and then stores the result into a destination register. In order to carry out this instruction, the designations of both the source (Rr) and the destination (Rd) registers need to be known.
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Opcode 11 is sent to the comparator, which outputs a value of 0
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A and B both go to the OR gate
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MUX3 output: A \(\vee\) B
