Microcontrollers

The architecture of a microcontroller refers to structure of its hardware and considers the relationship between the hardware and the machine instructions. A major motivating idea behind a microcontroller is that writing customizable software is much simpler than wiring up digital logic chips to implement a design. The tradeoff is that a microcontroller processor contains hardware that can carry out different operations based on the available instruction set. A more robust instruction set would therefore require more hardware in the central processing unit (CPU) to carry out additional instructions.

In the 1980s, reduced instruction set computing (RISC) CPUs began to be developed [16.11]. To contrast, some computers developed up to that point had very complicated instruction sets that required a lot of hardware to accommodate. These computers began to be known as using complex instruction set computing (CISC). The idea behind RISC architecture is that a CPU would include less hardware and fewer, more streamlined instructions. There was also a desire to prioritize an instruction set where each instruction could execute in no more than one clock cycle. As a result, even if the corresponding software algorithms used to generate complex outputs was longer, the faster hardware would lead to an overall reduction in compute time.

The bit-width of a microcontroller refers to the size of most registers and buses used in its design. For instance, an 8-bit microcontroller will typically have an 8-bit data bus, 8-bit registers, and be capable of operating on pieces of data eight bits at a time. (Larger values can be stored, but would need to be operated on in increments of eight bits.) While typical computers in use at the time of writing this book have a 64-bit architecture, many microcontrollers have a smaller bit width. Many consumer microcontrollers are either 8, 16, or 32 bits.

There are two main categories of CPU architectures used in computing devices. These are known as the Harvard architecture and von Neumann architecture. (This distinction is relatively complicated. Refer to [16.25] for a more nuanced discussion, which is otherwise beyond the scope of this textbook.) While both types of processors store program memory and data memory separately, the difference is in how the two types of memories are treated by the CPU.

In a Harvard architecture, program and data memory are treated as two distinct conceptual entities. Program memory and data memory have completely different addressing (input) and output signal paths. This allows the bit width of each type of memory to be different. (However, because bit width can be large, this is only feasible if program and data memory are stored on the same chip as the CPU, as otherwise the number of pins required in the package may be untenable if the bit widths are large for one or both types of memory.) The ATmega328P uses a Harvard architecture. A simplified block diagram of the Harvard architecture is shown in Figure 2.1.1.

In contrast, von Neumann architecture (named after mathematician and physicist John von Neumann) shares common program and data memory addressing signals and output signals. A simplified von Neumann architecture CPU block diagram is shown in Figure 2.1.2.