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Microcontrollers

Alyssa J. Pasquale, Ph.D.

Section 2.9 Instruction Execution Process and Timing

A microcontroller CPU is powered by a finite-state machine that fetches, decodes, and executes each instruction. In the process, the program counter must be incremented or changed to reflect the next instruction to execute. Control signals are generated to carry out the instruction and enable access to any areas where data is read from or written to. An example state diagram depicting this fetch, decode, and execution process is shown in Figure 2.9.1.
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State diagram. State 1 is labeled fetch instruction. State 2 is labeled decode instruction. State 3 is labeled PC increments. State 4 is labeled load data to registers. State 5 is labeled perform ALU operation. State 6 is labeled write data to memory/register/I/O. The transitions are: state 1 to state 2. State 2 to state 3. State 3 to state 4. State 4 to state 6 for instructions that don’t require the ALU (examples given are MOV, IN, OUT), otherwise to state 5 for instructions that do require the ALU (examples given are ADD, SUB). State 5 to state 6. State 6 to state 1.
Figure 2.9.1. State diagram of microcontroller instruction execution process.
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Each state is described below.
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  1. The next instruction in memory is read, indicated by the address stored in the program counter.
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  2. The instruction is decoded into a set of commands or signals for each of the components in the processor.
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  3. The program counter increments so that it points to the next location in memory.
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  4. Data is loaded from memory (or input device(s)) into register(s), the location of this data is usually stored in the instruction code as an operand.
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  5. If the ALU is required to execute the operation, the processor instructs the hardware to carry this out.
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  6. The result is written back to a memory location, to a register, or even to an output device.
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Some microcontrollers use a concept known as pipelining to speed up the rate at which the CPU can process the next instruction. The timing of this process is depicted in Figure 2.9.2.
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Five graphs plotted as a function of time. The top graph shows a clock signal with a constant period and duty-cycle of 50%. The next graph depicts the first instruction being fetched between the first and second rising clock edges. The next graph depicts the first instruction executing while the second instruction is fetched between the second and third rising clock edges. The next graph depicts the second instruction executing while the third instruction is fetched between the third and fourth rising clock edges, and so on.
Figure 2.9.2. Timing diagram of parallel instruction fetch process.
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