The status register (SREG) on the ATmega328P contains information about the result of the most recently executed instruction on the microcontroller. The information in SREG can be used to control the flow of the program being executed by way of conditional branch instructions (which is discussed in Section 15.3). All of the machine instructions that are capable of affecting the flags in SREG are listed in [16.15]. The status register contains eight bits (known as flags) as defined below.
Each individual flag can be set or cleared individually using a bit instruction as defined in [16.15]. In addition, the flags can be used with conditional (branch) instructions that can execute different code depending on whether a particular flag is set or clear.
Subsection4.3.1I: Global Interrupt Enable Flag (Bit 7)
The global interrupt enable flag (I) is used to enable and disable interrupts (as will be discussed in Chapter 8). It must be set to globally enable interrupts and it must be cleared to globally disable interrupts. This bit is automatically cleared by hardware on the ATmega328P when an interrupt service routine is invoked, and is subsequently set again when the execution of the ISR has been completed.
The half carry flag (H) is set when there is a carry from the least significant nibble (4 bits) in the most recently executed instruction. It is useful when dealing with binary coded decimal (BCD) numbers. In BCD arithmetic, the half carry has a value of 16. The most significant bit (MSB) of 16 (the number 1) belongs in the 10’s place of the BCD number. The remaining value of 6 needs to be added back in to the least significant nibble. An example of BCD addition where the half carry flag is set is shown in Example 4.3.1.
An algorithm for packed BCD addition (when two BCD digits are represented in an 8-bit binary number, as depicted in Example 4.3.1) is provided in [16.1].
The sign flag (S) is equal to an exclusive OR operation between the N and V flags. It gives the true sign of the result of the most recent operation, as described below.
Subsection4.3.5V: Two’s Complement Overflow Flag (Bit 3)
The two’s complement overflow flag (V) denotes whether or not overflow occurred with a signed arithmetic instruction. This bit is only generated with signed numbers. When set, the most recently executed operation resulted in an overflow condition. When cleared, the most recently executed operation did not result in an overflow. There are different equations for its generation based on the particular instruction that is in use.
In signed addition, an overflow occurs if the addition of two negative numbers results in a positive number, or when the addition of two positive numbers results in a negative number. Overflow is not possible when adding a positive to a negative number.
In signed subtraction, an overflow occurs if a positive number minus a negative number results in a negative number, or when a negative number minus a positive number results in a positive number. Overflow is not possible when subtracting a positive number from a positive number, or when subtracting a negative number from a negative number.
The negative flag (B) is used to determine if a signed value is positive or negative. This bit is only generated with signed numbers. The negative flag is the MSB of the result of the most recently executed operation. A value of 0 indicates a positive number, and a value of 1 indicates a negative number.
This carry flag (C) is set if the most recently executed operation resulted in a carry or a borrow. This flag is particularly useful when adding numbers that require more than 8-bits to store. For example, when adding 16-bit numbers, the microcontroller must work 8-bits at a time due to the size limitation of the CPU registers. A carry on the least significant byte (carry flag of 1) indicates that one must be added to the most significant byte.
