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Microcontrollers

Alyssa J. Pasquale, Ph.D.

Section 4.4 Peripheral Registers

Most peripherals on the ATmega328P are customizable by the user. This means that different features of each peripheral can be customized in the program code. This is accomplished by means of writing data to 8-bit peripheral registers. Some peripherals may also have registers that read or write some type of data. For example, the analog to digital converter (introduced in Section 6.4) has three registers used to configure the peripheral:
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  • ADC control and status register A (ADCSRA)
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  • ADC control and status register B (ADCSRB)
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  • ADC multiplexer selection register (ADMUX)
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Some of the individual bits in ADMUX are used to configure the analog voltage source and the analog reference voltage, as depicted in Figure 6.4.2.
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The analog to digital converter additionally uses two registers to store the output of the most recent conversion:
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  • ADC data register high byte (ADCH)
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  • ADC data register low byte (ADCL)
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Some bits in a peripheral register may be labeled as “reserved.” According to [16.14]: “[f]or compatibility with future devices, reserved bits should be written to zero if accessed.”
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The peripheral registers are stored in I/O and extended I/O data memory (described in Section 13.2). A list of all peripheral registers is included in [16.14].
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Subsection 4.4.1 16-Bit Registers

There are a few peripheral registers that are used to store 16 bits of information. All peripheral registers are stored in data memory, which has a word size of 8 bits. This means that the “16-bit registers” are in reality composed of two 8-bit registers and organized into high and low bytes. In particular, timer/counter 1 (introduced in Section 9.2) has multiple 16-bit registers to store the value in the 16-bit counter. There are a few important things to note when reading from or writing to these registers.
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Each read from or write to a 16-bit register must occur without interruption between the two bytes. If the process is interrupted between bytes, then it’s possible the contents of the registers can be modified during the interruption, which would cause the value written to or read from the second byte not to correspond to the data written to or read from the first byte. When reading from or writing to any 16-bit register, the global interrupt flag must be cleared to disable interrupts before the read or write operation. The global interrupt flag must then be set again after the read or write operation has concluded.
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When writing code in C using a compiler such as Atmel Studio or the Arduino IDE, each 16-bit register can be accessed directly. The compiler will then generate the corresponding assembly code to break the write or read into the two corresponding operations.
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Example 4.4.1. Writing to a 16-bit register in C.

The following code demonstrates writing to the timer/counter 1 output compare A register (OCR1A) using C. The cli() function globally disables interrupts and is used prior to writing to the 16-bit register. The sei() function globally enables interrupts and is used after writing to the 16-bit register.
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cli();
OCR1A = 0x3FA0;
sei();
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When writing code in assembly, the high and low bytes must be accessed separately. The following order of operations must be followed.
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  • Writing to a 16-bit register: write to the high byte before writing to the low byte.
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  • Reading from a 16-bit register: read from the low byte before reading from the high byte.
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Example 4.4.2. Reading from a 16-bit register in assembly.

The following code demonstrates reading from the timer/counter 1 register (TCNT1) using assembly. The CLI instruction globally disables interrupts and is used prior to reading from the register pair. The low byte is read prior to the high byte. The SEI instruction globally enables interrupts and is used after reading from the register pair.
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CLI
IN r16, TCNT1L
IN r17, TCNT1H
SEI
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The following 16-bit registers on the ATmega328P are composed of high and low bytes.
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  • ADC data register (ADC, composed of ADCL and ADCH), introduced in Section 6.4
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  • EEPROM address register (EEAR, composed of EEARL and EEARH), which is not discussed in this textbook
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  • Input capture register 1 (ICR1, composed of ICR1L and ICR1H), introduced in Section 9.7
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  • Output compare register 1 A (OCR1A, composed of OCR1AL and OCR1AH), introduced in Section 9.3
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  • Output compare register 1 B (OCR1B, composed of OCR1BL and OCR1BH), introduced in Section 9.3
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  • Stack pointer (SP, composed of SPL and SPH), introduced in Section 13.5
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  • Timer/counter 1 (TCNT1, composed of TCNT1L and TCNT1H), introduced in Section 9.2
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  • USART baud rate register (UBRR0, composed of UBRR0L and UBRR0H), introduced in Section 10.3
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